MBA Alumni | MBA Students | MBA Aspirants | MBA Forums
--- MBA Home ---

CoolAvenues.com

offers
Advertising
Services

on the web  
 

Home     |    MBA Jobs      |     Knowledge Zone      |     Seminars      |     Placement Report      |     Admission Alert       |     café     |     Search

IIM, Calcutta Organizes Workshop on the Latest Development of Nanometric Technology Regime

B - School News

 Home

 B-Schools' Home

 B-School News

 B-School Events

 B-School Diary

 Companies Research
 Center

 Career Resource Center

 Admission Alert

 MBA Forums

 Search
 Join e-Communities
 Buy Books
 Help Line!
 Mentor Program
 Be a CoolAssociate
 Give Suggestions

 Company Search
 
 

Subscribe:
GMAT list
  GMAT mailing list brings you tests, scholarships, news, developments & school admission alerts on a regular basi

So subscribe GMAT list and get the extra advantage!


Latest Discussion on CoolAvenues Forums

 

IIM, Calcutta Organizes Workshop on the Latest Development of Nanometric Technology Regime

IIM Calcutta organizes a one-day workshop on "VLSI Interconnect Routing in the Nanometric Regime" held at IIM Calcutta today in presence of Dr. Debesh Das, Minister in charge, Information Technology, Government of West Bengal who delivered the keynote address on "The Emergence and the Status of VLSI Activities in India".

The workshop was inaugurated by IIMC director, Prof. Shekhar Chaudhuri, Dean of Programme Initiative, Prof. Saibal Chattopadhyay, Project Head, Prof. Partha Sarathi Dasgupta, Chairman-FPR, Prof. Bhaskar Chakrabarti, Chairman - CMDP, Prof. Asish K. Bhattacharyya and Scientist, DIT, Ministry of Communication, Govt. of India, Y. S. Tanwar. This is the offshoot of the externally funded project under the title of Cost-Effective Tools for Routing of High-Performance Circuit Interconnects in Nanometric Technology Regime, sponsored by Department of Information Technology (DIT), Ministry of Communications and Information Technology, Government of India which is executed under Prof. Partha Sarathi Dasgupta and Debashis Saha of IIM Calcutta. In addition to the teaching programmes, management development programmes and research, IIMC is also engaged in numerous consultancy projects being funded externally.

The workshop also included lectures on various layers of the subject by distinguished speakers like prof. Partha Sarathi Dasgupta of IIM Calcutta on VLSI Routing in DSM Regime: Contributions of the IIMC project team, prof. Susanta Sen of University of Calcutta on Nano-scale devices: The future of Electronics, Prof. Hafizur Rahaman of Bengal Engineering & Science University on Test challenges for VLSI circuits in nanometric scales and Prof. Susmita Sur-Kolay of ISI Calcutta on Intellectual Property Protection of VLSI Design. More than sixty participants took part in this work shop. They represent the engineering students and professionals.

About the Project

The Annual Report of the International Technology Roadmap for Semiconductors (ITRS), 2002 has already identified the area of Nanometric Interconnects as a Long Term Grand Challenge. A highly relevant problem in this area is to Identify Solutions Addressing Global Wiring Issues. Some of the target problems in the proposed project will involve investigation of High-Performance Circuit Interconnects in Deep Sub-micron and Nanometric regime. The proposed research would broadly attempt to:-

  • Analyze critically the existing Global Routing algorithms for the Nanometric circuits
  • Concentrate on the development of practical solutions to have a faster layout design cycle
  • Invent efficient Global Routing algorithm(s) in Nanometric circuits with predictability for congestion, delay, crosstalk, heat dissipation, and buffer placement, and implement them
  • The objective of this project is to focus on the Nanometric interconnect design integrated with the related issues like buffer placement, congestion, crosstalk, heat dissipation and others. Specifically, the target problem would be as follows: Given a placement of logic modules and its associated netlist, construct buffer placement-aware Optimal Routing Trees for all nets such that the routing congestion, crosstalk, and heat dissipation are within specified bounds. Broadly, the aim of this project would be to help Indian research community come up with indigenous cost-effective tools for VLSI layout design. Efforts would be made to design and develop cost-effective methods, essentially special CAD (Computer Aided Design) tools, used for designing integrated circuit (IC) chips.

    Concluded.


    Send this article to Friend


    Contributed by -
    Aloke Guin,
    PRO,
    IIM, Calcutta.






    MBA Jobs
    MBA Preparation
    B-Schools
    MBA Forums
    About CoolAvenues
    Senior Mgmt Jobs CAT / MAT/ CET Dean talk CAT Preparation Post a Job
    Finance Jobs Admission Alert B-School Profile Executive MBA Advertise with Us
    Marketing Jobs MBA Insider B-School Diary Career Help Contact us
    HR MBA Jobs MBA Admission Process Summer GMAT Privacy
    Operations MBA Jobs English Preparation MBA News Companies Copyrights
    IT MBA Jobs MBA Abroad MBA Events B-Schools About CoolAenues
    Consulting MBA Jobs CAT / MAT / CET test papers MBA Placements Summer Guidance
    Resume Design Tips MBA in India Summers Guide Classifieds

    © All Copyrights exclusive with Zebra Networks
    Part or full of the contents can not be published, copied or reproduced
    in any form without the prior written exclusive permission of Zebra Networks. Pls refer to CoolAvenues Copyright section.